Calculating machines

ABSTRACT

An electronic calculating machine with two multistage registers and with circuitry controlled by an interchange function key on a keyboard are used to interchange the corresponding digit denominations of the numbers stored in the two registers. The interchange of each digit denomination is a two-part operation. In the first part a first pulse train is used to simultaneously circulate the digits in the corresponding denomination of the registers in order to store in a counter circuit a difference pulse count equal to the difference between the digits and to obtain a signal whose polarity is dependent upon which register has the larger digit. In the second part the difference pulse count and the polarity of the signal are used during the second pulse train to control the entry of part of the second pulse train to the one register and then to control the entry of the rest of the second pulse train to the other register so as to interchange the corresponding digits.

0 United States Patent 1151 3,641,501 Lloyd et al. 1 Feb. 8, 1972 s41 CALCULATING MACHINES 3,267,429 8/]966 Strohmeyer ..340/l46.2 3,273,122 9/1966 Chandler ....340/l46.2 [721 Uxbndge- 3,467,946 9/1969 Stefanik..... ....340/l46.2 Englmd 3,534,404 10 1970 Hanson...... ...........................235/l77 73 Assi ee: Bell Punch Compan Limited Uxbrid e, l 1 8n Enghmd y g Primary ExaminerPaul J. Henon Assistant Exanu'ner-Harvey E. Springbom Filed! Jim 1 1970 AnornyWatson, Cole, Grindle & Watson [21] Appl. No.: 5,221 [57] ABSTRACT Appum An electronic calculating machine with two multistage re- [63] confinuatiomimpm of No 526,049, Man 27 gisters and with circuitry controlled by an interchange func- |967 abandoned tion key on a keyboard are used to interchange the corresponding digit denominations of the numbers stored in the I! I n two registers. The interchange of each digit denomination is a [30] F0 AP Prior! mu two-part operation. In the first part a first pulse train is used to Mar. 31, 1966 Great Britain ......................l4,300/66 simultaneously circulate the digits in the corresponding denomination of the registers in order to store in a counter cir- [52] U8. CL ..340/l72.$, 340/l46.2 wit a difference p l count equal t he difference be ween 51 1m. (:1. ..G06t 7/02 the s and to obtain a signal whose P y is dependent [58] Field ofSearch ..340/172.5, 146.2; 235/177 P" which register has the larger s In the second P the difference pulse count and the polarity of the signal are used [56] 34cm CM during the second pulse train to control the entry of part of the second pulse train to the one register and then to control the UNITED STATES PATENTS entry of the rest of the second pulse train to the other register t t han th di di ts. 2,962,2ll 11/1960 Ghertman =1 al ..23s/61.1 was 0 m m ge ecmespm 81 3,238,356 3/1966 Dowds et a1. ..235I61.7 10 Claims, 5 Drawing Flgures CALCULATING MACHINES This is a continuation-in-part of my application Ser. No. 626.049 filed Mar. 27. I967, now abandoned.

BACKGROUND OF THE INVENTION Calculating machines are known which use a keyboard, a

visual register and two store registers. Numbers are entered from the keyboard into the visual register and these numbers may be transferred from the visual register into a selected one of the store registers. Arithmetical operations are performed on the numbers entered into the respective registers and the answers entered into the visual register. It sometimes happens, for example when it is required to carry out a divisional operation when the number entered in the visual register is divided by the number entered in the store register, that the numbers are entered in the wrong registers and it is desired to interchange these numbers. It is also sometimes required to be able to transfer the number entered in the visual register into a store register and restore the visual register to zero. Alternatively. it is required to be able to transfer the number entered in a store register to the visual register and to retain the number originally stored in the store register.

SUMMARY OF THE INVENTION A calculating machine having two registers for the storage of multidigit decimal numbers in which the decimal numbers in the registers can be interchanged by a two-part process which is repeated for each pair of corresponding stages of the register. In the first part of the twopart process, a train of IO pulses circulates the digits in a pair of corresponding stages and uses the carry pulse signal when each of the corresponding digits in the pair of corresponding stages passes through zero to store a pulse count equal to the difference between the corresponding digits in the pair of corresponding stages. A signal is also obtained whose polarity indicates which register has the larger digit. In the second part of the two-part process a second train of pulses is passed to the same pair of corresponding stages under the control of the stored difference pulse count and the polarity of the signal. The result is that the larger digit has a number of pulses from the second train of pulses equal to the difference pulse count added to it so that the larger digit is changed to the smaller digit. and the smaller digit has the remainder of the pulses of the second train of pulses of number equal to the complement of the difference pulse count added to it so that the smaller digit is changed to the larger digit. The first and second trains of pulses are consecutively applied to successive pairs of corresponding register stages including the corresponding pair of register stages which store the decimal point positions of the digits stored in the registers. The calculating machine has a gate circuit controlled by a key on the keyboard to modify the interchange operation to a clear and enter operation so that the numbers in one register can be transferred into the other register and a zero number is stored in the one register.

A calculating machine in accordance with the invention will now be described by way of preferred example with reference to the accompanying drawings, wherein:

FIG. 1 is a perspective view of an electronic calculating machine showing the keyboard;

FIG. 2 is a circuit diagram of part of the keyboard circuit of the calculating machine shown in FlG l',

FIG. 3 is a circuit diagram of part of the pulse supply part of the circuit ofthe calculating machine shown in FIG. I; and

FIG. 4 and 4a when taken together show a circuit diagram of a further part of the keyboard circuit and a part of the register circuits ol'the calculating machine shown in FIG. 1.

As shown in FIG. 1 of the drawings, a calculating machine has a casing 1 which includes a downwardly sloping front part 2 on which there is located a number keyboard It and a control keyboard 4. The control keyboard 4 has eight keys bearing the symbols I 'C+. x. RI and R2 respectively. The functions of the keys bearing the symbols i C+. RI and R2' are hereinafter described. Behind this desk-type front there is a vertical window 5 behind which there are arranged a plurality of number-indicating tubes 6, each of which serves to visually indicate the digit entered or stored in a respective register stage of a visual register of the calculating machine as will be hereinafter described.

A key 7 is included on the front part 2 to enable a decimal point to be included in the number entered into the machine. The position of the decimal point is shown on one of the indicator lamps 8. The position of the decimal point is stored as a pulse count in register stages VPDC or IPDPC hereinafter described. The decimal point pulse counts stored in the register stages correspond to illuminated indicator lamps; the zero decimal point pulse count causes the indicator lamp 8 on the extreme left-hand end of the calculating machine shown in FIG. 1 to be illuminated and the highest decimal point pulse count causes the indicator lamp in extreme right hand of the calculating machine shown in FIG. 1 to be illuminated. As hereinafter described, successive entry of digits into the calculating machine causes the decimal point to move successively in synchronism with the successive digits until movement of the decimal point is halted by operation of the key 7. A key 9 is included on the front part 2 to clear from the visual register, to be hereinafter described. a number entered into the register so that the number-indicating tubes 6 show a row of zeros.

The number keyboard 11 has l0 keys representing the digits 0 to 9 respectively. Each key representing one of the digits 1 to 9 is associated with and operates a respective key switch represented by the reference numbers l to '9 respectively in a bank of key switches Ila as shown in FIG. 40. Each key switch has two fixed contacts and a movable contact which is connected to one pulse of a group of pulses P1 to P9. One of the fixed contacts, which is normally not in contact with the movable contact. is connected to a keyboard output line 12. The other of the fixed contacts is connected to the movable contact of the key switch with the next higher reference number and, when the key switches are not operated is in contact with the movable contact. The movable contact of the key switch 9, which is operated by the key representative of the digit 9' is supplied with P9 pulses while the movable contact of the key switch 8' representative of the digit 8 is supplied with P8 pulses. The movable contacts of the other key switches have corresponding pulses supplied to them so that the movable contact of he key switch l representing the digit 1 is supplied with Pl pulses.

With reference to FIG. 3, pulse PO together with the pulses P1 to P9 supplied to the respective movable contact of the key switches l to 9' of the bank of key switches Ila are obtained from the ID outputs respectively ofa decade counter circuit in the form of the cathode circuits of a decade stepping tube 13. The cathode circuits of the stepping tube 13 are interconnected to form an output 9' which emits the pulses P1 to P9 in cyclic sequence. The stepping tube I3 is driven by oscillator pulses GD generated by a valve oscillator circuit [4 whose operation is controlled by an inhibit gate [3a which is an AND gate having the two inputs 5T3 and TO which are described later. When the inhibit gate l3a does not conduct. the grid of the valve of the oscillator circuit 14 is biassed so that oscillations. and hence the pulses PO to P9. are generated; and, when both inputs 5T3 and T0 are applied to the inhibit gate 130, the grid of the valve in the oscillator circuit 14 is biased to stop oscillating while both of the inputs are applied to the inhibit gate 130. The circuit of the decade stepping tube 13 is so arranged that only one cathode can conduct at any one time. Thus, assuming for example that the first cathode is conducting. this will mean that current flows through the circuit associated with this cathode and a connection is made to this circuit so that in this condition a pulse is generated along the line P0. On the supply of the next pulse to the decade counter circuit. the second cathode is caused to conduct while the first cathode ceases to conduct. and likewise, a pulse is caused to be generated along the line P1 and the pulse to the line P is cut off. Thus. on receipt of a further pulse the next succeeding cathode is caused to conduct and a pulse is passed to the line P2. This continues until the th i.e., the last cathode is conducting. A reference pulse P9 is then emitted and it is arranged that on receipt of the next subsequent pulse the 10th cathode will cease to conduct and the first cathode will start to conduct. By this means pulses P0 to P9 are sequentially and cyclically generated from the cathode circuits of the decade stepping tube counter circuit 13 and the pulses P1 to P9 are supplied to the key switches 1 to 9 respectively of the bank of key switches 110 (FIG. 4a). The pulse P9 emitted at the end of each sequence of 10 pulses is passed to a register time circuit (FIG. 3) and this register timer circuit is a circuit equivalent to the decade counter circuit 13 expect that it consists of 15 cathode circuits which generate the successive pulses TO, TD, T1 to T13 respectively. instead of pulses P0 to P9 of the decade counter circuit 13 and that it receives only one pulse P9 for every 10 pulses of the pulses applied to the decade counter 13. Thus. only onetenth of the number of pulses are applied to the register timer circuit 15, as to the decade counter circuit 13. It is arranged that the first pulse received by the register timer circuit causes the first stage of the timer circuit to conduct and a pulse to be generated on the line T0 and the receipt of subsequent pulses causes subsequent lines of the circuit to conduct. This will cause the respective pulses T0. TD. T1 to T3 to be sequentially and cyclically generated along the respective outputs. The input ST2 (to be hereinafter described) is connected to the register timer circuit 15. When the input ST2 is at a negative potential, the timer circuit 15 is held with the pulse T0 generated and. when the input 8T2 is changed to a positive potential. which occurs when the switch 3 or 22 (FlG. 2) is depressed. the pulse T0 is generated until the receipt of the next P9 pulse. The pulse P9 is passed to the register timer circuit 15 under the control of an inhibit gate 17. The gate 17 also controls the passage of P9 pulses through a gate 16 and a gate 19 whose outputs are connected to the input of a keyboard timer circuit 18. This keyboard timer circuit 18 is similar to the register time circuit 15, but has 13 cathode circuits and generates the pulses I] to I13. Receipt of successively gated P9 pulses by the keyboard timer 18 causes the pulses 11 to :13 to be generated in sequence.

The gate 16 is a three input AND gate having as the inputs the pulse line T0, the pulse line P9 and a line which is connected through a normally closed switch 110 to a source of negative potential. The switch 110 is operable for a short period when any one of the digit keys on the number keyboard 11, or when either of the keys bearing the symbols CE or 1 respectively is depressed. The gate 19 is a two-input AND gate having as the inputs the pulse line P9 and the pulse lines T1 through T13 respectively.

The inhibit gate 17 has the inputs C- and l (to be hereinafter described) and the pulse input T0, which is the inverted output of the pulse line T0, applied to it to control the entry of the P9 pulses to the register timer circuit 15 and to keyboard timer circuit 18.

The digit keys on the keyboard 11 are associated with a normally closed switch 22 (FIG. 2) which is connected to a negative potential and which is opened when a key on the keyboard is depressed. Similarly a normally closed switch 3 is connected in series with the switch 22 and is opened when a key of the control keyboard 4. other than the keys R1 and R2 is depressed. Opening the switch 3 or 22 causes the line STX connected to the operated switch 3 or 22 to go positive and also causes the delay circuits 23 and 24 to become operative to cause respective signals to be applied to the line ST3 and subsequently to the line 5T2. It will, therefore, be apparent that when the switch 3 or 22 is operated, theline STX will so positive and. alter delay period. positive potentials. are applied to the lines 5T3. ST2.

As shown in FIG. 4. the calculating machine includes a visual register 120 having a visual register decimal point counter VDPC and register stages R1 to R13. which are ring counters connected as decade pulse counters. whose inputs are connected to the outputs of two-input AND gates GDPC and RG1 to RG13. respectively. having one input connected to the pulse lines TD and T1 to T13 respectively. A highway line 121 is connected to the other inputs of the two-input AND gates GDPC and R013 connected to the counter VDPC and the register stages R1 to R13 respectively so that digit pulses transmitted along the highway line 121 are entered into that one of the counter VDPC or the register stages R1 to R13 whose one gate input has a pulse applied to it from the register timer circuit 15. As shown in FIG. 4a. the keyboard output line 12. which is connected to the bank of key switches 11a. is connected to an input of the input gate 151 which has an input supplied with a :12 pulse from the keyboard timer circuit l8 and which has the output connected to an input line 152. The input 152 is connected to the highway line 121 and to the register stages of the visual register 120.

The output of a two-input AND-gate is connected to the highway line 121. With continuing reference to FIGS. 4 and 4a, the gate 105 has as inputs the pulse line TD and a twobranch circuit respectively. One branch of the two-branch circuit comprises a register and a diode 106 in series which are connected between the input of the gate 105 and the keyboard output line 12; and the other branch of the two-part circuit comprises a normally open switch 107 which is connected between the input of the gate 105 and a source of negative potential. The switch 107 is closable by the depression of the decimal point key 7 (FIG. 1). When it is required to enter a digit ofa number into the visual register 120. the corresponding digit key (FIG. 1) is depressed and, in the bank of key switches 110. shown in FIG. 4a. the key switch associated with this digit key is operated so that the movable contact is moved into contact with the fixed contact connected to the keyboard output line 12. The pulses supplied to the movable contact are equal in number to the digit represented by the depressed digit key and are transmitted along the keyboard output line 12. For example. if the digit key representing the digit 4' is depressed, the movable contact on key switch '4 transmits the four pulses P1 to P4 along the keyboard output line 12. This number of pulses is passed along the line 12 to the gate 151. during each cycle of operation of the decade counter circuit 13 (FIG. 3). When the pulse :12 is received at the input of the gate 151 the arrival of the pulse on the line 12 serves to open the gate so that a train of oscillator pulses GD corresponding in number to the digit represented by the key depressed are transmitted along the highway line 152 and highway 121 to the visual register 120.

When the key corresponding to the first digit is depressed. the switch 22 is opened so that positive potentials appear on the lines STX, 8T2 and 8T3 so that the register time circuit 15. which is held with the line T0 energized, and the keyboard time circuit 18. which is held with the line r13 energized, are free to generate subsequent pulses. Since the input line I to the inhibit gate 17 is not energized. successive P9 pulses are passed to the register timer circuit 15 and to the keyboard timer circuit 18 under the control of the gates 16 and 19.

Since the switch of the gate 16 (FIG. 3) is closed for a short period when the key corresponding to the first digit is depressed, the gate 16 passes the first P9 pulse which causes the outputs TD and T1 of the register timer circuit 15 and the keyboard timer circuit 18 respectively to be energized. When the first digit is signalled, successive trains of pulses. all of which contain at least the pulse P1. are transmitted along the keyboard output line 12 through the diode 106 and to an input of the gate 105. The pulse TD is coincident with one of the pulses P1 so that the gate 105 passes a pulse which passes through the gate GDPC and into the decimal point counter VDPC to increase by one the pulse count corresponding to the decimal point position shown on one of the indicator lamps 8 (FIG. 1). When the decimal point position has reached the required position, the decimal point key 7 (FIG. 1) is depressed to close the switch 107 which reverse biases the diode 106 to isolate the closed gate 105 to any further P1 pulses.

The second P9 pulse is received by the register timer circuit 15 but is not received by the keyboard timer circuit 18 because the gates 16 and 19 are both closed which causes the pulse outputs l1 and T1 respectively to be energized. The next ten P9 pulses cause the respective register timer circuit 15 and the keyboard timer circuit 18 outputs T2 and !2 to T12 and ill respectively to occur in sequence and then a group of pulses equal in number to the first digit, is entered into the visual register stage R12. The visual register stage R13 is used only as a temporary store for carry pulses from the visual register stage R12. The next two P9 pulses from the input decade counter 13 cause the register timer circuit 15 to energize the lines T13 and T0 and cause the keyboard timer circuit 18 to energize the r13 and :1 respectively. Since the inputs T0 and 3T3 of the inhibit gate 13a are energized. the inhibit gate 13a stops the operation of the oscillator 14 and stops the generation of further P9 pulses by the input decade counter 13.

As hereinafter described, the depression of the interchange key I on the control keyboard 4 opens the switch 3 to initiate an interchange operation during which an identical operation of the output Tines of the register timer circuit 15 and the keyboard timer circuit 18 occurs as described for the depression of the first digit key on the digit keyboard 11.

When the key corresponding to the first digit is released, the negative potential reappears on the lines STX, 8T2 and 8T3 so that the oscillator 14 resumes the generation of oscillator pulses GD and so that the line T0 of the register timer circuit remains energized. Because the output T0 remains energized. the gates 16 and I!) prevent P9 pulses from reaching the keyboard timer circuit 18 so that the output 11 remains energized. Subsequent digits of the number are entered in the succeeding right hand register stages R to R1 because the timer pulse :12 corresponds to successively lower pulses of the register timer circuit at each succeeding entry ofa digit of the number so that the digits of the number are entered in sequence from left to right. Each time the pulses T0 and 5T3 are received by the inhibit gate 13a, the gate will operate to switch off the oscillator 14. The register stages R1 to R12 of the visual register are each associated with a circuit including a number-indicating tube 6 to indicate the digit stored in the corresponding register stages.

Two store registers 123 and 122 have register stages r13 to r3 and store register decimal point counters IPDPC and have respective gates I613 to r63, rDPC and r613 to r63 and rDPC controlled by pulses (13 to r3 and TD. :1 respectively. The store registers 122. 123 are similar in construction and operation to the visual register 120 and are also included as stores into which digits may be transferred from the visual register 120 stage by stage as hereinafter described. The gate 100, which is a two-input gate having the inputs TD and 11, controls the operation of the two gates rPDC. rPDC' so that the gates rDPC, rDPC of the store registers 122 and 123 are operated at the same time as the gate GDPC of the visual register as hereinafter described. A switch 124 determines which of the store registers 122, 123 is to receive digits transferred from the visual register 120. A key I on the control keyboard (FIG. 1) sets in operation the interposing of the digits of a number entered in the visual register 120 with the digits of a number entered in the selected one of the store registers 122, 123. The key 1 opens the switch 3 (FIG. 2) and applies a positive voltage to the gates (to be hereinafter described) at the positions showing the symbol. Each stage of the visual register 120 is connected to the highway line 121 which serves as an input to it.

A visual register flood gate 125 (FIG. 4a), is connected to the highway line 152 and to the highway line 121 and serves to control the entry of the continuous train of pulses GD supplied from the oscillator 14 to the line highway 121 to be transmitted to the various stages of the visual register in a continuous train when the switch key i is depressed.

The counter VDPC and the register stages R1 to R13 each have a carry output which is energized when the count in the counter or stage is stepped from the 9 count to the 0 count. The carry outputs are connected together and are connected to the set input of a carry store bistable circuit 126. The carry store bistable circuit 126 has outputs C01 and C01 and has a reset input which is connected to the PO pulse line of the input decade counter 13. The output C01 is raised to a positive potential when the digit count stored in a visual register stage connected to an energized pulse line from the register timer circuit 15 is stepped to the zero count by pulses transmitted along the line 121. The output C01 is lowered to a negative potential by the action of the next P0 pulse so that the output C01 remains at a positive potential until a carry output stage of the visual register is energized.

Similarly. a store register flood gate 127 (FIG. 4) is connected to an input to the store registers 122, 123 to control the entry ofa continuous train of pulses supplied on the line GD to the store register when the 1 switch key is depressed and the input Cis energized during the first half of the cycle ot'operation.

Each stage of the store registers 122, 123 has a carry store output which is connected to the set input of a carry store bistable circuit 128 which has the outputs C02 and C02 and which is identical in construction and operation to the carry store bistable circuit 126 previously described. As previously described, the output C02 of the carry store bistable circuit 128 is raised to a positive potential when the digit stored in the counter IPDPC or a register stage r3 to r13 ofa store re gister is stepped to a zero digit.

With reference to FIG. 4a, a difference-sensing gate 129. to sense when the number stored in a store register is greater than the number stored in the visual register, is connected to a line 159 and is connected to the input of an exchange bistable circuit 131. A difference-sensing gate 130 to sense when the number stored in the visual register is greater than the number stored in the store register is connected to line 159 and is also connected to the inputB of the exchange bistable circuit 131.

The line 159 is also connected to a gate 142 which has the inputs C+ and B e O (to be hereinafter described). The exchange bistable circuit 131 has a pair of lines B 0; y. A buffer decade counter circuit 135 comprises a ring counter circuit connected as a decade counter circuit which when the line 159 is raised in potential by the gate 129, 130 or 142. counts oscillator pulses GD transmitted along the line 159. The decade counter circuit which. when the line 159 is raised in potential by the gate 129, 130 or 142, counts oscillator pulses GD transmitted along the line 159. The decade counter circuit of the bufi'er circuit 135 has an output B=0 which is connected as an input to an inverter circuit circuit 144. The output B r 0 of the inverter circuit 144 is connected as an output to the exchange bistable circuit 131.

Each of the gates 130 129 have applied to them the pulses C01, C02, and C02, F C01, respectively. These pulses are representative of the carry signal given off from the respective stage of the visual register and of the stages of the store register and can be representative of the difierence between the numbers stored in the visual register and store register. Thus, if, as hereinafter described, a series often pulses is simultaneously applied to the corresponding register stages of the visual register and a store register to circulate the digits therein when the digit stored in a register stage is counted up to zero, a carry pulse will be emitted and passed to the respective carry store circuit 126, 128 This carry signal is passed to the respective gate 129, 130 and the respective gate opens the pass the signal to the exchange bistable circuit 131. Thus, if the gate 129 is opened first this indicates that the digit stored in the store register is greater than the digit stored in the visual register. Consequently. the pulses are passed from the gate 129 to the input a of the exchange bistable circuit 131 and in this condition the line y becomes positive. If, on the other hand the digit stored in the visual register is greater than the digit stored in the store register, a similar condition will arise except that the pulse C01 will be given off before the pulse C02 and the gate 130 will open before the gate 129, in which case a signal will be passed to the other input [3 to the exchange bistable circuit 131 and the line y will become negative.

The connection y is an input to a gate 132 whose other inputs are I C+, and CE (hereinafter described). The outputs of the gate 132 is connected through a diode 133 to a transistor inverter circuit 134 and inverts the output of the gate 132. The output of the inverter 134 is connected to the highway 121. When the gate 132 is opened (line y positive), the inverter circuit 134 prevents the transmission of pulses along the highway line 121, and vice versa.

The buffer circuit 135, which is connected to the gates 129, is also connected to the gate 130, a source of oscillator pulses GD and a gate 142. When a carry pulse C01 or C02 is received on the respective gates 129 or 130, this gate will be opened and will permit pulses to be passed to the buffer decade counter circuit 135. By this means the difference between the numbers entered in the visual and store registers is determined as a pulse count stored in the buffer decade counter circuit 135.

A gate 135a, is arranged to supply pulses, which are equal either to the number or to the complement of the number of pulses stored in the buffer decade counter circuit 135, to the corresponding register stages of the visual register and a store register to increase the count of these register stages by the difference or the complement of the difference between the digits originally stored in the store register and the digit originally stored in the visual register 120.

A bistable circuit 136 has an input which is operated by the signal STX (FIG. 2) and an input which is the output of a gate 137 whose inputs are the pulses P9, T and I. The bistable circuit 136 has the outputs C-, C+. when a positive potential appears on the line STX, the output C- is energized. It is arranged that, during a first batch of ten pulses the difference between the digits in the corresponding register stage of a store register and the visual register are sensed during the time when the bistable circuit 136 has the output C- energized and that during a second batch of IO pulses it is arranged to enter correction pulses to the register stages of the store and visual registers, so that the digits stored in the corresponding register stages of the registers are interchanged during the time when the bistable circuit 136 has the output C+ energized. The two batches of H) pulses are generated by using the bistable control gate 137 to control bistable circuit 136 which in turn controls the entry of alternate P9 pulses through the inhibit gate 17 into the circuit and circuit 18.

Depression ofthe key 3 opens the switch 3 (FIG. 2) to cause the generation of TD and T1 to T13 pulses simultaneously with the generation of I] and t1 to I13 pulses respectively as previously described, but each step will require two P9 pulses.

To effect switching off of the pulses to be applied to the stages of the visual register 120 after these stages have been returned to zero, a gate 150 and a gate 155, are included. These gates are connected to the reversal circuit 134 which in turn is connected to the highway 12]. The gate 150 is an OR gate with the inputs T1, T2 and CE; the gate 155 is an AND gate with the inputs C01, 1 and C+. If the gate 150 is not operative, then unless the pulse C01 is received and unless the! and C+ connects are positive, the gate 155 is closed and, because of the inverter circuit 134, pulses will only be allowed to pass to the highway 121 before the pulse C01 is received.

If the pulse T1 or T2 is applied to the input of the gate 150 or if the CE input goes positive because the key CE (FIG. 1 is depressed to clear the number in the visual register into a store register, the gate 150 will close to prevent the transmission of any pulses along the highway line 121 while the gate 150 is closed.

When in operation a number has been entered in the various stages of the visual register 120 as previously described and a number is then cleared from the visual register I20 and entered in the various stages of a selected store register as described later, it may be desired to interchange the numbers stored in the respective registers i.e., the digits in the visual register stages VDPC and R3 to R13 are interchanged with the digits in the corresponding selected store register stages lPDPC and r3 t0 r13 respectively. To effect this interchange, the interchange key I is depressed. The interchange lines I are connected and also open the switch 3 (FIG. 2) to initiate the simultaneous generation of pulses in the register timer circuit 15 and the keyboard timer circuit 18 previously described. The line STX ensures that the output 0- of the bistable circuit 136 is energized at the beginning of the interchange operation. The energizing of the interchange lines 1 serves to open the visual register flood gate to cause oscillator pulses GD from the input line GD on the line 152 to pass to the stages of the visual register 120. At the same time, a positive potential is applied to the store register flood gate 127 which permits oscillator pulses GD supplied from the input line GD to pass to the stages of the selected store register 122 or 123. The oscillator pulses GD being in synchronism, the two respective paths pass to the respective registers 120, 122 together. The first digits to be interchanged are the digits in the visual register decimal point counter VDPC and a store decimal point counter IDPC but, because the description is simpler, the second digits to be interchanged, the digits in the visual register stage R3 and a store register stage r3, will be described in detail. The first group of IO pulses is passed to the register stage r3 and R3 of the respective registers (because of the effect of gate 150) and each pulse drives a digit stored in these register stages from the initial digit value to the next higher digit and up to zero and back to the initial digit value again. As the oscillator pulses GD enter the register stage R3 of the visual register they cause the digit entered to be passed through zero. A carry pulse is emitted as the digit passes through zero and this is signalled as a positive potential on the output C01 from the carry store circuit 126. Likewise. as the train of oscillator pulses CD is passed to the register stage r3 of the store register, a carry pulse is emitted as the digit passes through zero, and this likewise is passed to the carry store circuit 128 and is signalled as a positive potential on the output C02. The pulses C01 and C02 are passed to the respective gate inputs C01 C02, of the respective difference sensing gates 129, 130. If a positive potential is received by the gate input C01 before a positive potential is received by the gate input C02 (because the digit in the visual register is higher) a positive potential will be passed along they line to the exchange bistable circuit 131 and the line y will become negative, similarly, if the gate input C02 receives a positive potential first (because the digit in the store register is higher) a positive potential will be passed along the carry line a to the exchange bistable circuit 131 and the line y will become positive.

Initially the gate inputs a C01 and C02 are at apositive potential and the inputs C01 and C02 are at a negative potential. If the gate input C01 receives a positive potential before the gate input CO2, the sensing gate raises the potential of the line 159 so that oscillator pulses GD are transmitted along the line 159 to enable the buffer decade counter circuit 135 to count the number of oscillator pulses GD transmitted along the line 159. However, when the gate input C02 receives a positive potential, the gate input e C02 of the gate 130 receives a negative potential so that the gate 130 ceases to raise the potential of the line 159. The change in potential of the line 159 stops any further supply of pulses to the buffer decade counter circuit 135. Hence, the buffer decade counter circuit will store a pulse count equal to the difference in the number of pulses stored in the corresponding register stages R3 and r3 of the visual register and store register respectively. Depending on which of the lines a or]! has been energized, the potential of line y will determine which of the register stages has the larger digit.

At the end of receipt of nine pulses, the pulse P9 is sent to the gate 137 which passes the pulse to the bistable circuit 136 and causes the output to switch over to energize the C+ output. When the C+ output is energized, the C+ signal is passed to the input C+ on the gate 142 which, if the input B is energized because a nonzero pulse count is stored in the buffer decade counter circuit 135, will energize the line 159, so that the decade counter circuit of the buffer circuit 135 will count the second group of [0 pulses until the input B=0 is energized. The C+ signal is applied to the input C+ of the gate 132 and if the number stored in the visual register is greater than the number stored in the store register, the line y will become negative so that the gate 132 is closed. In this gate condition the transistor of the transistor inverter circuit 134 ceases to conduct and allows the complement of pulse count stored in the buffer decade counter circuit 135 to be passed into the register stage R3 of the visual register which now stores the digit originally stored in the store register stage r3. However, on emission of the carry pulse B=0 from the buffer decade counter circuit 135, the inverter circuit 144 emits an output which changes the output of the bistable circuit 13] to cause the line y to change polarity and go positive.

The positive value for the line y causes gate 132 to open and the inverter circuit 134 to block the highway line 121 so that the remainder of the pulses during the C+ cycle do not enter the visual register, but because the y input is positive, the remainder, ie, the complement of the IQ pulses, are passed to the drive circuit gate 135a and the addition of the complement of the second group of 10 pulses is entered in the store register to change the stored pulse count to that originally stored in the visual register.

If, on the other hand, the digit stored in the store register stage is greater than the digit stored in the visual register stage, a reverse operation will take place and the pulse count stored in the buffer decade counter circuit 135 during the first group of 10 pulses is entered in the visual register during the second group of 10 pulses and the complement of this pulse count stored in the decade counter circuit 135 is entered in the store register.

This operation is repeated for each pair of corresponding register stages R4 and r4 to R13 and r13 of the visual register and the store register respectively until all the digits stored in the one register are transferred into the visual register into the store register and vice versa.

As previously mentioned the first digits which are actually interchanged are the digits in the visual register decimal point counter VCPC and in a store register decimal point counter IPDOC, which digits represent the decimal point positions of numbers stored in the respective registers. This first interchange operation occurs when the output TD of the register timer circuit is energized in synchronism with the output r] of the keyboard timer circuit 18, so that the gate [00 energizes the gate circuits GDPC of the store registers at the same time as the timer pulse TD energizes the gate circuit GDPC of the visual register. The interchange operation is otherwise identical to the interchange operation previously described.

When it is required to clear a number from the visual register and enter this number into a preselected store register, the CE. key on the keyboard 4 (FIG. 1) is depressed to cause the input v CE to change from a positive to a negative potential. The clear and enter operation of the machine is basically the same as for effecting the interchange operation except that the input I CE is negative so that the gates 132 and 150 are open and the inverter circuit 134 is controlled only by gate 155. When the input C01 of the gate 155 receives a positive potentiai during the entry of the second group of 10 pulses, the gate 155 is opened to cause the transistor of the transistor inverter circuit 134 to conduct so that the line U1 is blocked and the remainder of the second group of 10 pulses is prevented passing to the visual register so that the digit zero is stored in the visual register stage. The digit originally stored in the visual register stage is transferred into the corresponding store register stage in the same manner as previously described.

What is claimed is l. A calculating machine, comprising:

a first register and a second register wherein numbers entered into the machine are stored,

first gate means for entering a train of pulses into corresponding stages of both registers for circulating the digits stored therein,

means to emit a carry pulse as the digit in each corresponding register stage passes through a predetermined digit value,

means for sensing the position of the carry pulses of each register stage with respect to respective trains of pulses to determine the digits stored in the corresponding stages of said registers,

means for generating a train of difference pulses having a number of pulses equal to the difference in the digits stored in the corresponding register stages of said first and second registers and means for adding said train of difference pulses and a pulse train of number equal to the complement of the number of pulses in the trains of difference pulses to respective selected corresponding stages of each register so that the original digits stored in the corresponding selected stages of each register are interchanged.

2. A calculating machine, comprising;

a first register and a second register wherein numbers entered into the machine are stored,

first gate means for entering a train of pulses into the pair of register stages of the register which contain digits of corresponding denomination to circulate the digits stored therein,

means to emit a carry pulse as the circulated digit in each register stage of said pair of register stages of the register which contains digits of corresponding denomination passes through a predetermined digit value,

means for sensing the position of the carry pulses of the circulated digits with respect to the train of pulses to determine the relative magnitude of digits stored in said pair of register stages,

means for generating a pulse or a train of pulses of pulse number equal to the difference in the digits stored in said pair of register stages, and

means for adding a pulse or a train of pulses of pulse number equal to the number of pulses in the train of difference pulses and a pulse or a train of pulses of pulse number equal to the complement of the number of pulses in the train of difference pulses to said pair of register stages respectively of the register which contain digits of corresponding denomination so that the original digits stored in said pair of register stages are interchanged.

3. A calculating machine according to claim 2 where said digit of corresponding denomination include digits whose magnitudes are proportional to the decimal point positions in the numbers stored in the corresponding registers.

4. A calculating machine according to claim 2 wherein said means for generating a pulse or a train of pulses includes a first train of pulses which provides a first pulse or group of pulses equal to the difference between the digits stored in the corresponding stages of said registers and a second pulse or group of pulses, said pulses of the second group being respectively equivalent to the complement of respective pulses of the first group, and wherein said means for adding enters said first group of pulses into said stages of said pair of registers and enters said second group of pulses into said stage of the other of said pair of registers to effect the interchange of the original digits stored in said pair of stages of said registers.

5. A calculating machine according to claim 4 wherein said sensing means includes decade counter means for determining the difference between the digits stored in said pair of register stages of said registers,

said means for generating a pulse or a train of pulses being responsive to said decade counter means, and second gate means for entering said first and second group of pulses into said pair of register stages of said registers to effect the interchange of said original digits.

6. A calculating machine according to claim 4 wherein said first gate means circulates the digits stored in said pair of register stages of said registers back to their initial digits. said means for adding enters pulses from said first group of pulses into the register stage of said pair of register stages of said registers having the lower initial digit and entering pulses from said second group of pulses into the register stage of said pair of register stages of said registers having the higher original digit to effect digit interchange.

7. A calculating machine according to claim 6 wherein said sensing means includes counting circuit means responsive to a first carry pulse from one register stage of said pair of register stages to start counting and responsive to a second carry pulse from the other register stage of said pair of register stages to stop counting to determine the differences between the digits stored in said pair of register stages.

8. A calculating machine according to claim 6 wherein said sensing means includes means for determining the register stage of said pair of register stages having the higher digit entered therein.

9. A calculating machine according to claim 7 further comprising means for gating a number of pulses corresponding to the respective difference counts in said counting circuit means to the register stage of said pair of said register stages having the lower digit and means for gating a number of pulses corresponding to the respective complements of the respective difference counts in said counting circuit means to the register stage ofsaid pair of register stages having the higher digit.

10. A calculating machine according to claim 6 further comprising timing circuit means for controlling the gating of the pulses successively into said pair of register stages of said registers. 

1. A calculating machine, comprising: a first register and a second register wherein numbers entered into the machine are stored, first gate means for entering a train of pulses into corresponding stages of both registers for circulating the digits stored therein, means to emit a carry pulse as the digit in each corresponding register stage passes through a predetermined digit value, means for sensing the position of the carry pulses of each register stage with respect to respective trains of pulses to determine the digits stored in the corresponding stages of said registers, means for generating a train of difference pulses having a number of pulses equal to the difference in the digits stored in the corresponding register stages of said first and second registers and means for adding said train of difference pulses and a pulse train of number equal to the complement of the number of pulses in the trains of difference pulses to respective selected corresponding stages of each register so that the original digits stored in the corresponding selected stages of each register are interchanged.
 2. A calculating machine, comprising; a first register and a second register wherein numbers entered into the machine are stored, first gate means for entering a train of pulses into the pair of register stages of the register which contain digits of corresponding denomination to circulate the digits stored therein, means to emit a carry pulse as the circulated digit in each register stage of said pair of register stages of the register which contains digits of corresponding denomination passes through a predetermined digit value, means for sensing the position of the carry pulsEs of the circulated digits with respect to the train of pulses to determine the relative magnitude of digits stored in said pair of register stages, means for generating a pulse or a train of pulses of pulse number equal to the difference in the digits stored in said pair of register stages, and means for adding a pulse or a train of pulses of pulse number equal to the number of pulses in the train of difference pulses and a pulse or a train of pulses of pulse number equal to the complement of the number of pulses in the train of difference pulses to said pair of register stages respectively of the register which contain digits of corresponding denomination so that the original digits stored in said pair of register stages are interchanged.
 3. A calculating machine according to claim 2 wherein said digit of corresponding denomination include digits whose magnitudes are proportional to the decimal point positions in the numbers stored in the corresponding registers.
 4. A calculating machine according to claim 2 wherein said means for generating a pulse or a train of pulses includes a first train of pulses which provides a first pulse or group of pulses equal to the difference between the digits stored in the corresponding stages of said registers and a second pulse or group of pulses, said pulses of the second group being respectively equivalent to the complement of respective pulses of the first group, and wherein said means for adding enters said first group of pulses into said stages of said pair of registers and enters said second group of pulses into said stage of the other of said pair of registers to effect the interchange of the original digits stored in said pair of stages of said registers.
 5. A calculating machine according to claim 4 wherein said sensing means includes decade counter means for determining the difference between the digits stored in said pair of register stages of said registers, said means for generating a pulse or a train of pulses being responsive to said decade counter means, and second gate means for entering said first and second group of pulses into said pair of register stages of said registers to effect the interchange of said original digits.
 6. A calculating machine according to claim 4 wherein said first gate means circulates the digits stored in said pair of register stages of said registers back to their initial digits, said means for adding enters pulses from said first group of pulses into the register stage of said pair of register stages of said registers having the lower initial digit and entering pulses from said second group of pulses into the register stage of said pair of register stages of said registers having the higher original digit to effect digit interchange.
 7. A calculating machine according to claim 6 wherein said sensing means includes counting circuit means responsive to a first carry pulse from one register stage of said pair of register stages to start counting and responsive to a second carry pulse from the other register stage of said pair of register stages to stop counting to determine the differences between the digits stored in said pair of register stages.
 8. A calculating machine according to claim 6 wherein said sensing means includes means for determining the register stage of said pair of register stages having the higher digit entered therein.
 9. A calculating machine according to claim 7 further comprising means for gating a number of pulses corresponding to the respective difference counts in said counting circuit means to the register stage of said pair of said register stages having the lower digit and means for gating a number of pulses corresponding to the respective complements of the respective difference counts in said counting circuit means to the register stage of said pair of register stages having the higher digit.
 10. A calculating machine according to claim 6 further comprising timing circuit means for controlling the gating of the pulses successively iNto said pair of register stages of said registers. 